Computer Architecture

.. Speed means that how long it takes the memory in nano-seconds to retrieve the data. Standard memory speeds have not progressed at same rate as processor speeds. As a result, the CPU can process data faster than the data can be fetched from memory or placed in memory. The Pentium motherboard operates at no more than 66MHz while CPUs can run at up to 266MHz.

Consider that a 133MHz CPU cycles every 7ns while the access time for main memory is usually 70ns. Accessing each cell will incur the same circuit switching time overhead. This is the chip’s access time. There will be address lines and also data lines to transfer data in and out of the cells to the CPU. A data transfer will either be a read operation (the cell’s contents are copied on to the data bus) or a write operation (the contents of the data bus are copies into the cells). To instruct the chip, on which operation is required, it is fed read/write information on its control lines. If the CPU requires data from memory, it issues a read instruction along with the address to be read.

To write data to memory, the CPU places the data on the data bus and issues a write instruction along with the address location. 3. The term ALU stands for Arithmetic Logic Unit this carries out all the arithmetic and logical operations with in the CPU or Central Processing Unit. The term Register covers the areas of transient storage, which hold information keep track of instructions and retain the position and results of these operations. Each of the different registers has a specific purpose of what functions that it has to carry out they are located in the Execution Unit. There is a number of registers which carry out certain functions, e.g.

memory address register, memory buffer register, stack pointer, program counter and the process status register. The term Control Circuit is used to control many of the computer’s other components such as the memory and the periheral devices. It has an interrupt unit that indicates the order in which particular operations use the CPU, also it limits the amount of CPU time each operation may take /tells them what it wants to do. There is an instruction decoder that reads the pattern of information in a specific register and decodes the pattern into an operation. The term Control Bus is when data travels between the CPU and memory on parallel wires called a bus.

One line contains the control signals that are generated from within the CPU. Another line senses the input signals. Every bus operation begins with a new clock tick. The term Address Bus is what is used to locates information in memory addresses, its a one way line from the processor, Each memory location has an individual address, the CPU accesses a particular address by putting the specific address in binary format on to the address bus. The term Data Bus is what is used to transfer data between the CPU and memory by a two way transfer that can read information or write new information into memory when the correct memory location is found, but its only able to write the new information to RAM memory.

MEMORY CPU 1- MEMORY ADDRESS (ADDRESS BUS) 2 – CONTROL SIGNAL (CONTROL BUS) 3- DATA (DATA BUS) 1- Knocking on door to open it. 2- Transfer the data. 3- Telling it what it wants to do. 4. The diagram on the last page shows how CPU registers are used, the diagram is called the Fetch / Execute Cycle, and there is two main parts, the fetch cycle and the execute cycle. These cycles can be divided into a more specific description of how the registers are used, the fetch part of the cycle is the same regardless of the instruction but the instructions will change in the execute part of the cycle.

This cycle can be broken down into a more detailed account of how the various registers are used they are detailed below. Registers, are specialized storage areas, these are used to hold information temporarily while it is being decoded. Each of these registers has a defined purpose to carry out so that the computer can operate effectively. A General-purpose registers that are used for performing arithmetic functions. A Current instruction registers that contain both the operator and the operand of the current instruction.

The Program Counter is the register that holds the address of the next instruction to be carried out these instruction are automatically incremented to the next ‘instruction. But when the current instruction is a branch or jump instruction, then that address is copied from the instruction to the Program Counter. The Program Counter is copied to the Memory Address Register which hold the address of the memory locations from which information will be read or to which data will be written and occasionally. It will hold the address of the instruction in the fetch cycle and the information to be used in an instruction in the execute cycle. Memory data registers are used to temporarily store information read from or written to the memory. Data goes here before it goes to the Current Instruction Register where it is decoded.

Once the instruction has been decoded the operand of the instruction is put in the MAR and the data will then be copied to the MDR. Any transfers of data from memory go via the MDR. The MDR and the MAR serve the system as screen registers, this allows for the difference in speed between the CPU and the memory. The CIR or Current Instruction Register is where the instruction is copied to it holds both the operator and the operand of the current instruction If the Fetch / Execute cycle is interrupted by more information then it will stack the cycle between the fetch and execute phase then deal with the new data and return to the interrupted cycle. The test for interrupts is only carried out at the end of each instruction cycle.

When the item in the MDR is added to the Accumulator the whole operation carries on returning to the fetch cycle. The Accumulator is the register that carries out arithmetical functions. The status registers contain bits that are carried bases on the result of an instruction. They also contain information on interrupts to information to get a priority on less important information. All these steps are added to the program counter. Between each stage of this cycle the data is carried on busses that take it to the address part or the data part of the cycle.

There are different types of bus here are two examples. The Address Bus carries addresses so that the required locations can be accessed so they can read or write data. The Data Bus transfers the information to the correct memory location. This then means from the diagram the fetch part of the cycle carries all the data to the correct one of the execute part of the cycle. The fetch part of the cycle is common while the execute part of the cycle varies. The fetch-execute cycle is as follows: The address of the instruction is copied from the PC and held in the MAR.

The instruction (e.g., add x), is placed into the MDR where it is temporarily stored. The instruction (add x), is then copied to the CIR. The PC now moves on to the next instruction, (e.g., add y). While in the CIR the instruction is decoded, this determines what the instruction has to do, (add). The operand part of the instruction, (x) is then copied to the MAR. The data item (e.g., 3), whose address is still stored in the MAR, is copied to the MDR.

The item held in the MDR (3) is then added to the accumulator. The process is then repeated for the next instruction, (add y). The accumulator works as follows: For example, value x = 3, y = 4, z = 7 Instructions – add x, add y, add z Accumulator Value = 0 ” = 3 ” = 7 ” = 14 The root of the single cycle processor’s problems: The cycle time has to be long enough for the slowest instruction (load) Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle Cycle time: time it takes to execute the longest step Keep all the steps to have similar length Use a register to save a signal’s value whenever a signal is generated in one clock cycle and used in another cycle later The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete Load takes five cycles Jump only takes three cycles Allows a functional unit to be used more than once per instruction (though requires more muxes, registers) Well, the root of these problems of course is that facts that the Single Cycle Processor’s cycle time has to be long enough for the slowest instruction. The solution is simple. Just break the instruction into smaller steps and instead of executing an entire instruction in one cycle, we will execute each of these steps in one cycle.

Since the cycle time in this case will then be the time it takes to execute the longest step, our goal should be keeping all the steps to have similar length when we break up the instruction. Well the last two bullets pretty much summarise what a multiple cycle processor is all about. The first advantage of the multiple cycle processor is of course shorter cycle time than the single cycle processor. The cycle time now only has to be long enough to execute part of the instruction (point to “breaking into steps). But may be more importantly, now different instructions can take different number of cycles to complete.

For example: (1) The load instruction will take five cycles to complete. (2) But the Jump instruction will only take three cycles. This feature greatly reduces the idle time inside the processor. Finally, the multiple cycle implementation allows a functional unit to be used more than once per instruction as long as it is used on different clock cycles. For example, we can use the ALU to increment the Program Counter as well as doing address calculation. Computers and Internet.